Integrated circuits generally include an electrostatic discharge (ESD) device for shunting currents which occur during the manufacturing process (e.g. due to discharging of a charged human body (‘human body model’, or ‘HBM’)). In pad-based ESD designs, in particular, the ESD protection is usually placed locally, and is connected to the drains of an output stage MOS. During an ESD event, current shunting occurs after a trigger voltage across the ESD device has been reached. When the ESD device triggers, its voltage drops to a holding voltage. The trigger voltage of the ESD device should therefore be above a maximum operating voltage of the product.
A challenge related to pad-based ESD design is that the ESD protection device often has a higher trigger voltage than the trigger voltage of a driver MOS device to be protected. Triggering of the MOS devices may thus occur earlier than triggering of the ESD device when the gate voltage of the driver MOS is uncontrolled and unknown during an ESD event. An early trigger of the MOS device is unwanted because it may lead to immediate failure.
Silicon controlled rectifiers are often used as an ESD protection device for pad-based ESD protection. The current shunting capacity per unit of area of SCR's is typically superior to that of gate-grounded NMOS (ggNMOS) devices. However, traditional SCR designs typically have a trigger voltage that is too high to be usable in many designs.
Furthermore, an SCR typically has low holding voltage (i.e. the voltage at which the current shunting mode operates, after triggering the SCR), which can lead to latch-up during testing or thereafter when an ESD event occurs. Latch-up generally leads to device failure.
Various approaches have been taken in the past for tuning the trigger and holding voltages of an SCR, leads to designs including Medium Voltage Silicon Controlled Rectifiers (MVSCRs) and Low Voltage Silicon Controlled Rectifiers (LVSCRs).